The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a redundant memory, and more specifically, to a redundant address selection apparatus for designating a redundant memory cell.
In a conventional semiconductor memory device having a redundant memory, when a normal memory cell is defective, an address not for the defective normal memory cell but for the redundant memory is selected.
FIG. 5 shows the conventional semiconductor memory device having a redundant memory. In FIG. 5, a predecoder 62 decodes row address signal bits A0B to A5B and outputs address selection signal bits X11 to X14, X21 to X24, and X31 to X34 to array interconnections (to be described later). A normal address decoder 63 outputs a normal cell word for designating a specific normal memory cell array of a normal memory 64 on the basis of the address selection signal bits X11 to X14, X21 to X24, and X31 to X34 on the array interconnections.
The address (defective address) of the defective normal memory cell which has been found in the wafer test process is programmed in a program circuit 61. If an address signal for designating the defective address is input, the program circuit 61 outputs an inactivating signal called a killer signal K for setting the normal memory cell in the normal memory 64 in a nonselection state and simultaneously outputs redundant address signals SX1 and SX2 to select redundant memory cells in a redundant memory 66 in place of the defective normal memory cell.
FIG. 6 shows the arrangement of the predecoder 62. Referring to FIG. 6, the predecoder 62 comprises three predecoder units 621 (A), 622 (B), and 623 (C). Each of the predecoder units 621 to 623 receives two bits of the six row address signal bits A0B to A5B and outputs the four address selection signal bits X1 to X14, X21 to X24, or X31 to X34 to the array interconnections.
As shown in FIGS. 7A and 7B, these predecoder units 621 to 623 are constituted by logic circuits comprising a plurality of logic gates for receiving the address signal bits A0B to A5B. The predecoder unit 622 is constituted by a plurality of inverters and NOR gates, as shown in FIG. 7B. The predecoder unit 622 calculates the logic between the row address signal bits A2b and A3B and the killer signal K to inactivate the normal memory 64. In other words, the predecoder unit controls the normal address decoder 63 to set the normal memory cell in the normal memory 64 in a nonselection state. Reference numeral 622a denotes an arithmetic circuit for determining selection of the normal memory 64 or a redundant memory 66 on the basis of the killer signal K.
More specifically, when the normal memory cell in the normal memory 64 is to be selected, the program circuit 61 sets the killer signal K at "H" level, and the outputs X21 to X24 from the predecoder unit 622 are set at values determined by the row address signal bits A2B and A3B. When the normal memory cell in the normal memory 64 is to be set in the nonselection state, the killer signal K of "L" level is input to the predecoder unit 622, and all the outputs X21 to X24 are set at "H" level independently of the values of the corresponding row address signal bits A2B and A3B.
FIG. 8 shows the arrangements of the normal address decoder 63 and a redundant address decoder 65 and their relationship with the array interconnections. In FIG. 8, the array interconnections comprise normal address selection signal lines 68 corresponding to the address selection signal bits X11 to X14, X21 to X24, and X31 to X34 from the three predecoder units 621 to 623, and redundant address selection signal lines 69 corresponding to the redundant address selection signals SX1 and SX2 output from the program circuit 61.
The normal address decoder 63 has a plurality of NOR gates 631i each of which receives one output from each of the three predecoder units 621 to 623. In response to the outputs from the NOR gates 631i, memory cell word drives (WD) 632i corresponding to the normal memory cell arrays designated by the row address signal bits A0B to A5B are driven, so normal cell words are output to the normal memory 64.
When the redundant memory 66 is to be selected, since all the four outputs X21 to X24 from the predecoder unit 622 are set at "H" level, all the NOR gates 631i constituting the normal address decoder 63 output signals of "L" level. With this operation, the normal memory 64 is not selected but inactivated. At this time, the redundant address selection signals SX1 and SX2 output from the program circuit 61 are input to the redundant address decoder 65 through the redundant address selection signal lines 69.
In the redundant address decoder 65, redundant memory cell word drives (RWD) 652a and 652b are driven on the basis of the redundant address selection signals SX1 and SX2 obtained from the redundant address selection signal lines 69, so redundant cell (RED) words 1 and 2 are output to the redundant memory 66. With this operation, predetermined redundant memory cell arrays of the redundant memory 66 are selected.
In the conventional semiconductor memory device, the redundant address selection signal lines 69 for sending the redundant address selection signals SX1 and SX2 which are output from the program circuit 61 to the redundant address decoder 65 to select redundant addresses must be arranged to the array interconnections in addition to the normal address selection signal lines 68. For this reason, as the number of redundant memory cells increases, the number of redundant address selection signal lines 69 also increases. Consequently, the number of array interconnections increases, resulting in an increase in chip area.